Title: ASIC/FPGA Design Verification Engineer with UVM Experience
Create UVM simulation plan from design specification. Create or modify UVC, Score Board, Monitor, and test cases. Verify until functional coverage and code coverage meet project threshold. Document results.
Education / Experience:
Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, computer science, mathematics, physics or chemistry (e.g. Bachelor) and typically 5 or more years' related work experience or an equivalent combination of technical education and experience (e.g. PhD, Master+3 years' related work experience). In the USA, ABET accreditation is the preferred, although not required, accreditation standard.
Additional Comments:
Please make sure the below information is included in the comment section or top of candidates resume for consideration. Candidates without this info listed as requested will be rejected.
Is your candidate local to El Segundo?
If your candidate is not local are they relocating at their own expense?
Are they aware this position is 100% onsite?
Does your candidate have experience with UVM? How many years?
Does your candidate have 5 years of ASIC/FPGA Design Verification Engineer experience manager will reject if candidates does not?
Does your candidate hold a Bachelor’s Degree in Engineering, if not please do not submit? They’ll be rejected)
Export Compliance requires U.S Citizen, Does this candidate meet this requirement?
Position Comments:
PLEASE ONLY SUBMIT CANDIDATES WHO ARE FULLY COMMITTED TO WORKING ONSITE 100% AND 6 MONTHS ASSIGNMENT.
PLEASE READ AND REVIEW ALL JOB DETAILS, INCLUDING ADDITONAL INFO REQUIRED BEFORE SUBMITTING. THIS WILL PREVENT REJECTIONS FOR MISSING INFO OR INCORRECT EMAIL. WE WILL NOT EXTEND/INCREASE SUBMISSION LIMITS, UNTIL WE ALLOW THE OPPORTUNITY FOR ALL SUPPLIERS TO SUBMIT.
Required Skills
1-2 years of UVM tool
5+ years of experience
Cadence Xcelium verification tool
Max bill rate: Approved to submit over the high, but at the managers discretion.
Shifts: First
Onsite/remote/hybrid: 100% Onsite
U. S CITIZEN REQUIRED (NO DUAL CITIZENSHIP)
Education: Must have min Bachelor’s in Engineering (no exception, please do not submit candidates without)
Additional Details: Must have min 5 years of experience, please do not submit without, manager will reject (he’s interviews are thorough and so is his resume review, please thorough screen candidates). UVM experience is important and required. Manager highly likely to consider extending contract or converting the right candidate in future.
Successful completion of training is a contingency for this assignment – OJT or formal classroom training
Porterville, California